Cadence Design Systems expanded its ChipStack AI Super Agent platform with a new tool that automates front-end digital chip design. This agent generates and refines Register-Transfer Level (RTL) code directly from natural language specifications.
The tool aims to increase productivity while optimizing power, performance, and area (PPA). In early evaluations, the RTL Generation Agent achieved a 24% average reduction in chip area. It also reduced power consumption by 18% compared to standard foundation models.
This release advances the company’s strategy to create agentic AI workflows that function as virtual design engineers. Cadence expects to provide these capabilities to select customers in Q4 2026.